The first goal of this project is to identify nanoscale size effects that deteriorate thermal management of devices and circuits as their feature dimensions continue to shrink. The second goal is to develop theoretical models and computer simulation tools for description of confined acoustic phonon transport through multi-layer medium, which constitutes a device structure or chip + interconnect system. A particular focus of this research is acoustic phonon spectrum modification at nanoscale and effects of phonon confinement on the lattice thermal conductivity.